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Two-Core MESI State Machine

Follow a single cache line through Exclusive, Shared, Modified, and Invalid states as two cores read and write it.

Core 0 L1Core 1 L1coherence fabricEIline state in Core 0line state in Core 1coherence eventRead miss serviced from LLC or DRAMCore 0 has the only clean copycounter = 0
Step 1 / 5Core 0 reads the line first

No cache has the line yet, so Core 0 fetches it and becomes the only clean owner.

M
single dirty owner
E
single clean owner
S
shared clean copies
I
no valid cached copy

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